A bipolar semiconductor device has conventionally been used for high-withstand-voltage uses such as a pn-junction diode formed using silicon (Si) as the semiconductor material. This is because, in the pn-junction diode, injection of minority carriers causes variation of the conductivity of the drift layer and thus, internal resistance can be reduced significantly though the built-in voltage of the junction is high compared to that of a unipolar semiconductor device such as a Schottky barrier diode. For high-withstand-voltage uses, a drift layer of a semiconductor device is set to be thick and has a high resistance. Consequently, use of a pn-junction diode capable of reducing stationary loss is advantageous. However, the pn-junction diode has a large amount of accumulated carriers remaining in the drift layer when a switching operation thereof is turned off and therefore, significant time is consumed for the accumulated carriers to vanish and the reverse recovery current thereof becomes large. Consequently, problems arise in that the switching speed of the pn-junction diode becomes slow and the switching loss becomes large.
To solve these problems, a complex diode has been proposed that is formed by combining the pn-junction diode and a diode having a built-in potential that is lower than that of the pn-junction diode. The diode having the built-in potential that is lower than that of the pn-junction diode is a Schottky barrier diode, or a shallow pn-junction diode including a p-layer that is shallower than a p-layer constituting the pn-junction diode and having an impurity concentration that is lower than that of the p-layer constituting the pn-junction diode (hereinafter, “shallow p-n layer”).
More specifically, such diodes have been proposed and fully utilized as: an Si complex diode having an MPS (Merged Pin/Schottky) structure formed by combining pn-junctions and Schottky barriers as depicted in FIG. 18 (an MPS diode) and an Si complex diode having an SFD (Soft and Fast recovery Diode) structure formed by combining a pn-junction and a shallow p-n junction as depicted in FIG. 19 (an SFD diode).
FIG. 18 is a cross-sectional diagram of a conventional complex diode. A low-withstand-voltage MPS diode depicted in FIG. 18 has an n−-epitaxial layer to be an n− drift layer 182 disposed on the anterior surface of an n+-Si substrate 181. P-n junction barriers and Schottky barriers are present on the surface of the n−-drift layer 182. More specifically, multiple p+-regions 183 are selectively disposed in the surface layer of the n−-drift layer 182, and pn-junctions are formed by alternating and repeated disposition of the n−-drift layer 182 and the p+-regions 183.
A Schottky contact 184 is formed on the anterior surface of the Si substrate 181 and is in contact with the p+-regions 183 and the drift layer 182. An ohmic contact 185 is disposed on the posterior surface of the Si substrate 181 and is in contact with the Si substrate 181. The P+-regions 183 formed in the outmost portions each extend to a junction termination extension (JTE) region 190. A passivation film 191 is disposed on the anterior surface of the Si substrate 181 and covers the n−-drift layer 182 that is exposed in a portion of each of the p+-regions 183 at ends and the junction termination extension regions 190.
In the above MPS diode, an operation of the Schottky conjunction diode is dominating in a small-current region and a low forward voltage is obtained while an operation of the pn-conjunction diode is dominating in a large-current region and a forward voltage is obtained that is lower than that of the Schottky barrier diode. Therefore, compared in all the current regions, the stationary loss is reduced. In the MPS diode, the majority of the accumulated carriers remaining in the drift layer are discharged through the Schottky barrier when the switching operation is turned off and therefore, the accumulated carrier vanishing time period can be shortened. As a result, the MPS diode is characterized by a high switching speed and low switching loss (see, e.g., Nonpatent Literature 1).
FIG. 19 is a cross-sectional diagram of another example of a conventional complex diode. An SFD diode depicted in FIG. 19 has an n-epitaxial layer to be an n-drift layer 202 disposed on the anterior surface of an n+-Si substrate 201. A p-n junction barrier and a shallow p-n junction barrier are present on the surface of the n-drift layer 202. More specifically, a p+-region 203 is selectively disposed in a surface layer of the n-drift layer 202, and a pn-junction is formed by the n-drift layer 202 and the p+-region 203.
In the surface layer of the n-drift layer 202, a shallow p-region 204 is selectively disposed that is shallower than the p+-region 203 and has an impurity concentration that is lower than that of the p+-region 203. The shallow p-region 204 is in contact with the p+-region 203. The Schottky contact 205 is formed on the anterior surface of the Si substrate 201 and is in contact with the p+-region 203 and the shallow p-region 204. An ohmic contact 206 is disposed on the posterior surface of the Si substrate 201 and is in contact with the Si substrate 201. The SFD diode has a breakdown voltage of, for example, a 600-V class.
In the above SFD diode, an operation of the shallow pn-conjunction diode is dominating in a small-current region while an operation of the pn-conjunction diode is dominating in a large-current region. Therefore, in the large-current region during use, a significant conductivity variation of the pn-junction diode and a low forward voltage are obtained and thus, a low stationary loss is maintained similarly to a diode including only a pn-junction. On the other hand, in the SFD diode, the majority of the accumulated carriers remaining in the drift layer are discharged through the shallow pn-junction when the switching operation is turned off and the accumulated carrier vanishing time period can be shortened. As a result, the SFD diode is characterized by a high switching speed and low switching loss compared to the diode including only a pn-junction. The SFD diode enables the reverse recovery current to be reduced and the recovery time to be extended (soft recovery) and therefore, the SFD diode is characterized by applicability to an inverter, etc., and suppressed generation of noise (see, e.g., Nonpatent Literature 2).
Wide-gap semiconductor materials such as silicon carbide (SiC) have recently drawn attention as semiconductor materials suitable for high-withstand-voltage uses. For example, SiC has an excellent property of a high insulation-breakdown electric field intensity that is about 10 times as high as that of Si, and SiC realizes a high reverse-voltage blocking property. When a pn-junction diode is configured using SiC that is a bipolar semiconductor device, the diode realizes performance that is far more excellent compared to that of a pn-junction diode configured using Si. For example, when a pn-junction diode configured using SiC has a high withstand voltage of 10 kV or higher, the forward voltage of this diode is about a quarter or smaller and the reverse recovery time period corresponding to the speed obtained when the diode is turned off is about 10% or less, compared to those of a pn-junction diode configured using Si. Therefore, the pn-junction diode configured using SiC performs switching operation at high speeds and enables power loss to be reduced to about ⅙ or smaller than that of the pn-junction diode configured using Si. Therefore, wide-gap semiconductor materials such as SiC is expected to significantly contribute to energy saving (see, e.g., Nonpatent Literature 3).
An apparatus has been proposed as a semiconductor device configured using a wide-gap semiconductor material. In the apparatus, a junction formed by a drift layer and an anode layer, and a field limiting layer of a bipolar semiconductor device are formed isolated from each other, and an end of an anode electrode is disposed facing a semiconductor region between the junction and the field limiting layer through an insulating film. When a reverse bias is applied to the semiconductor device, the junction and the field limiting layer are electrically connected to each other due to an electric field effect given from the electrode through the insulating film to a drift layer between the junction and the field limiting layer, and concentration of the electric field is alleviated at an end of the junction. When a forward bias is applied thereto, the junction and the field limiting layer are also electrically isolated from each other and a forward current is caused to flow only through the junction (see, e.g., Patent Document 1).
An apparatus has been proposed as a semiconductor device having a Schottky barrier formed therein, including: a semiconductor substrate having a first surface and a second surface, a first conductivity type cathode region adjacent to the first surface, and a first conductivity type drift region on the cathode region; a cathode electrode in contact with the cathode region; a first trench disposed on the second surface, having a first side wall in the drift region, and having a mesa that is disposed between the first side wall and a second side wall and that has a predetermined mesa width and a predetermined mesa doping concentration; a second trench disposed on the second surface and having a second side wall in the drift region; a first insulating region on the first side wall and a second insulating region on the second side wall; an anode electrode disposed on the second surface and the first and the second insulating regions and forming a Schottky rectifying junction together with the mesa on the second surface, and the predetermined mesa doping concentration is higher than 1×1016 dopant/cm3 (see, e.g., Patent Document 2).
A 600-V-class low-withstand-voltage MPS diode has recently been proposed as depicted in FIG. 18, that uses SiC as a wide-gap semiconductor material, the properties of which are disclosed (see, e.g., Nonpatent Literature 4).    Patent Document 1: Japanese Laid-Open Patent Publication No. 2005-223220    Patent Document 2: Japanese Laid-Open Patent Publication No. 08-512430    Nonpatent Literature 1: The Institute of Electrical Engineers of Japan, “Power Device IC Handbook”, 1st Edition, Corona Publishing Co., Ltd., Jul. 30, 1996, pp. 97-98    Nonpatent Literature 2: Mori, M., et al, “A NOVEL SOFT AND FAST RECOVERY DIODE (SFD) WITH THIN P-LAYER FORMED BY AL—SI ELECTRODE”, (US), Proceedings of 3rd International Symposium on Power Semiconductor Devices and ICs, 1991, pp. 113-117    Nonpatent Literature 3: Sugawara, Yoshitaka, “SiC Power Devices for High-Power Conversion”, Applied Physics, The Japan Society of Applied Physics, 2001, Vol. 70, No. 5, pp. 530-535    Nonpatent Literature 4: Alexandrov, P., et al, “4H—SiC MPS Diode Fabrication and Characterization in an Inductively Loaded Half-Bridge Inverter up to 100 kW”, (Switzerland), ICSCRM '01: Proceedings of International Conference of Silicon Carbide and Related Materials 2001, Oct. 28 to Nov. 2, 2001, pp. 1177-1180